Method for making an electronic component with self-aligned drain and gate, in damascene architecture

ABSTRACT

The invention concerns a method for fabricating an electronic component with self-aligned source, drain and gate, comprising the following steps:  
     a) forming a dummy gate on a silicon substrate ( 100 ),  
     b) forming a source ( 118 ) and drain ( 120 ) either side of the dummy gate,  
     c) self-aligned, superficial siliciding of the source and drain,  
     d) depositing at least one, so-called contact, metal layer ( 130, 132 ),  
     e) replacing the dummy gate by at least one final gate ( 150 ).

TECHNICAL FIELD

[0001] The present invention concerns a method for fabricatingelectronic components with self-aligned source, drain and gate. Thecomponents concerned by the invention may be insulated gate transistorssuch as MOS transistors (Metal Oxide Semiconductor) for example, orelectronic memories with a dual gate, that is to say with a command gateand a floating gate.

[0002] The method of the invention particularly concerns the fabricationof these components on a solid silicon substrate or on a thin layersubstrate such as a substrate of SOI type (Silicon on Insulator).

[0003] The invention finds applications in numerous microelectronicareas, ranging from power switching to hyperfrequency circuits, notforgetting memory circuits.

STATE OF PRIOR ART

[0004] Methods for producing transistors using self-aligning techniquesare known, for example, from documents (1) and (2) whose references aregiven at the end of this description.

[0005] Document (1) in particular, concerns the fabrication of a MIStransistor (Metal Insulator Semiconductor). It describes a methodaccording to which a dummy gate is used to fix the location and size ofa final gate that is subsequently formed. The final gate is preferablyin a material having low resistivity, such as metal for example, so asto reduce gate resistance and to increase the cut-off frequency of thetransistor.

[0006] Document (2) indicates a method which suggests siliciding thesource and drain regions, so that the source and drain accessresistances can also be reduced. The method of document (2) remainsrelatively complex however.

DISCLOSURE OF THE INVENTION

[0007] The invention sets out to propose a method for fabricatingcomponents which is different to the methods described in the documentsindicated above, and with which it is possible to further reduce gate,source and drain resistances.

[0008] Another purpose is to put forward such a method whose applicationis simplified.

[0009] A further purpose is to make available such a method which allowsgreater miniaturization of the components and therefore greater circuitintegration.

[0010] Finally, another purpose, connected with the above aspects, is toput forward a method with which it is possible to obtain transistorshaving a particularly high cut-off frequency.

[0011] To achieve these purposes, the subject of the invention is moreprecisely a method for fabricating an electronic component withself-aligned source, drain and gate, comprising the following steps:

[0012] a) forming a dummy gate on a silicon substrate, said dummy gatedefining a location for a channel of the component,

[0013] b) implanting doping impurities in the substrate, to form asource and drain either side of the channel, using the dummy gate asimplanting mask,

[0014] c) self-aligned superficial siliciding of the source and drain,

[0015] d) depositing at least one, so-called contact, metal layer, whosetotal thickness is greater than the height of the dummy gate, andpolishing the metal layer stopping at the dummy gate.

[0016] e) replacing the dummy gage by at least one final gate, separatedfrom the substrate by a gate insulating layer, and electricallyinsulated from the source and drain.

[0017] By means of the contact metal layer, but also on account of theself-aligned siliciding of the source and drain, the access resistanceof the source and drain may be particularly reduced despite the verysmall dimensions of the component.

[0018] In addition, by having recourse to a dummy gate, it is possible,at the end of the method, to obtain a final gate that is self-aligned onthe source and drain regions. This type of structure is particularlysuited to reduced component sizes, and in particular to gate lengths ofless than 0.10 μm.

[0019] According to one particular embodiment of the method, theformation of the dummy gate may advantageously comprise the depositingof a first layer of material, a so-called stress adaptation layer, andof a second layer of material, a so-called polish stop layer, and theforming of these layers by etching using a mask defining the dimensions,the shape and positioning of the gate.

[0020] At first view the essential role of the dummy gate is simply to“reserve a site” for the final gate that is subsequently made. However,the choice of a dual-layer dummy gate facilitates the subsequent stepsof the method. The first layer is preferably a layer having acoefficient of thermal expansion and an average mesh parameter close tothat of the material of the substrate. For monocrystalline siliconsubstrates, the stress adaptation layer may therefore, for example, be alayer of amorphous or polycrystalline silicon. In addition, thedepositing technique for these materials is easy to implement and wellknown.

[0021] The material of the second layer may, preferably, be chosen tohave good resistance to abrasion and polishing. It therefore providesfor better use of the dummy gate as stop mark during the polishingoperation of the contact metal.

[0022] According to another aspect of the invention, the sides of thedummy gate may be lined with one or more layers of side spacers. Bylayer of side spacers is meant a layer of dielectric material whichlines the side walls of a gate, that is to say the sides substantiallyperpendicular to the substrate carrying the gate. Advantage may be takenof the layers of side spacers when forming the source and drain, byusing them as additional implanting masks. The use of side spacers forimplantation, known in itself, makes it possible to obtain source anddrain regions having gradual impurity concentrations.

[0023] Within the scope of the invention, when placed in position beforesiliciding, the spacers also protect the dummy gate from siliciding, andprovide for a greater choice of materials for the latter.

[0024] Finally, the side spacers may advantageously be used in theremainder of the method as electric insulating means for the final gatefrom the layer of contact metal.

[0025] The side spacers may be single layer spacers or, preferably,twin-layer spacers. Here again, a first layer of silicon oxide makes itpossible to limit contact stresses with the gate and substrate—thespacers effectively coming into contact with a small portion of thesubstrate. A second layer of silicon nitride on the other hand is welladapted to protecting the dummy gate both against oxidation and againstsiliciding.

[0026] Step d) mentioned above for depositing the contact metal may,according to one improvement, include the depositing of a first layer ofmetal then, on top of the first layer, the depositing of a second metallayer having mechanical resistance to polishing that is greater thanthat of the first layer. The thickness of the first metal layer istherefore chosen to be smaller than the height of the dummy gate.However, the total thickness of the first and second layers is greaterthan the height of the dummy gate.

[0027] The purpose of the second metal layer is to reduce the so-called“dishing” phenomenon of polishing. This phenomenon leads to fastererosion of the polished material in the higher step regions than in thelow regions. In other words, the depositing of two contact metal layersunder the above-described conditions makes it possible, after polishing,to obtain a free surface having excellent planarity.

[0028] The contact metal, or at least the first layer of this metal,extends the source and drain providing for very low access resistance tothese regions.

[0029] When polishing reaches the top of the dummy gate, or starts toenter it, it produces separation in the gate region of the metal incontact with the source from the metal in contact with the drain.Further etching (which does not directly form part of the method of theinvention) makes it possible to cut the contact metal outside the activeregion crossed by the gate, and hence to complete the electricinsulation between drain and source.

[0030] The layers of contact metal are formed before the replacement ofthe dummy gate by the final gate. Therefore, in order to prevent thematerial of the final gate, preferably having low resistivity, fromshort-circuiting the source and drain, it is necessary to provide forsurface insulation or the contact layers in the source and drainregions. This operation could optionally be conducted by depositing alayer of dielectric material. According to one particular aspect of theinvention however, the method may comprise superficial oxidation of themetal layers. Oxidation can provide a simple, sure guarantee of electricinsulation between source, gate and drain. In addition it avoids anymasking operation.

[0031] In the subsequent steps of the fabrication of the component, itis possible to make openings in the oxide of the contact metal layers toinsert contact points for interconnection lines.

[0032] The removal of the dummy gate may comprise one or more selectiveetching operations to remove its component layers. This is followed bythe placing in position of a gate insulation layer on the substrate, inthe well left by the dummy gate.

[0033] A following step consists of placing in position one or morelayers of conductor material, or at least having low resistivity,optionally separated by a dielectric layer. These layers form one ormore gates.

[0034] More precisely, when the component it is desired to produce is atransistor, one or more conductor layers are provided to form a singlegate.

[0035] On the other hand, if the desired component is a memory, it ispossible firstly to deposit a first conductor layer and then a secondconductor layer, separated from the first conductor layer by a layer ofdielectric material. The first and second conductor layers thenrespectively form the floating and command gates. The dielectric layerforms an inter-gate insulating layer.

[0036] It is to be specified that the conductor and dielectric layersmentioned above may be homogeneous or they may be formed of stacks ofseveral sub-layers.

[0037] The layer or layers which form the gate structure are preferablydeposited with an overall thickness that is the same as or more than theheight of the removed dummy gate, so as to be able to undergo polishing.

[0038] Other characteristics and advantages of the invention will becomeapparent on reading the following description, with reference to thefigures of the appended drawings. This description is solely given forillustrative purposes and is non-restrictive.

SHORT DESCRIPTION OF THE FIGURES

[0039] FIGS. 1 to 3 are illustrations, in the form of diagrammaticcross-sections, showing the fabrication steps for a component with adummy gate.

[0040] FIGS. 4 to 5 are cross-section diagrams illustrating theformation of source and drain accesses for a component according to FIG.3.

[0041]FIG. 6 is a cross-section diagram of a component according to FIG.5 and illustrates an electric insulating step of the source and drainaccesses.

[0042] FIGS. 7 to 9 are cross-section diagrams illustrating thereplacement of the dummy gate by a final gate.

[0043]FIGS. 10 and 11 are cross-section diagrams illustrating a variantof the steps in FIGS. 8 and 9 for fabricating another type of component.

[0044]FIG. 12 is a cross-section view of a portion of an integratedcircuit with components according to the invention, and illustrates thefabrication of an interconnection.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0045] Identical, similar or equivalent parts in the figures describedbelow carry the same numerical references so as to facilitatecross-referencing from one figure to another. Also, even though thefollowing description only concerns the fabrication of components on asolid substrate, in silicon in this case, it is to be emphasized thatthe methods remain the same for forming components on insulated thinlayer substrates, such as substrates of SOI type (Silicon On Insulator).

[0046]FIG. 1 shows a silicon substrate 100 whose surface has beenoxidized in order to form a silicon oxide layer 102, a so-calledpedestal layer.

[0047] On layer 102 are successively deposited a layer ofpolycrystalline or amorphous silicon 104, then a layer of siliconnitride 106. These layers together form a stack 110. The total thicknessof layers 104 and 106 is in the order of 100 to 300 nm for example, andsubstantially corresponds to the thickness of the transistor gate whichis finally obtained at the end of the method of fabrication.

[0048] An etching mask 108, shown in a dashed line, such as a mask ofphotosensitive resin, is formed on layer 106 of silicon nitride. Thismask defines the positioning, the size and the shape of a dummy gatewhich it is desired to fabricate in stack 110.

[0049] Layers 102, 104 and 106 of stack 110 are removed by etching, withthe exception of a portion protected by the mask 108.

[0050] This portion of the stack forms the body of the dummy gate,referenced 112 in FIG. 2.

[0051] The formation of the dummy gate is followed by a first ionimplantation at low dose. Depending upon whether the component it isdesired to produce is of PMOS or NMOS type, the ions are chosen so as tomake zones of p or n type conductivity. They may for example be boronions for PMOS components and phosphorus or arsenic ions for NMOScomponents.

[0052] The first implantation is followed by the formation of sidespacers 114, 116 on the side or sides of the dummy gate, visible in FIG.2.

[0053] The side spacers comprise a first layer of silicon oxide 114 incontact with layers 104 and 106 of the dummy gate and a second,superficial, layer 116, of silicon nitride covering the oxide layer. Thepurpose of the first spacer layer 114 is essentially to limit contactstresses with the layers of material of the dummy gate, and especiallywith the polycrystalline silicone. It also limits the contact stresseswith a small portion of substrate which it touches at the base of thedummy gate.

[0054] The role of the second spacer layer is essentially to protect thedummy gate from subsequent treatments in the method, in particular fromoxidation treatments.

[0055] The formation of the side spacers may be made using techniquesknown in themselves which for the most part comprise the depositing ofselected materials over the entire wafer, followed by anisotropicetching of these materials so as only to leave a small thickness on thesides of the dummy gate.

[0056] Optionally, after the formation of the side spacers, a secondimplanting of impurities may be conducted at a higher dose. The secondimplanting then uses the dummy gate, widened by the side spacers, asimplantation mask. With this second implanting it is possible to obtaingradual source and drain regions 118, 120 in the substrate, with dopingwhich decreases towards channel 121 located under the dummy gate 112.The gradual nature of the source and drain regions is not shown in thefigures for reasons of clarity.

[0057]FIG. 3 shows a following step which consists of performingselective siliciding of the substrate in the source and drain regions.This operation comprises the depositing of a metal layer 124 such as,for example, titanium or nickel, followed by heat treatment atsufficient temperature to cause a siliciding reaction between the metaland silicon of the substrate.

[0058] Siliciding is qualified as selective insofar as it is limited tothe zones in which the metal of layer 124 is directly in contact withsilicon. It can be seen in FIG. 3 that the metal layer 124 hasdisappeared above the source and drain regions to form superficiallayers of silicide 126, 128. On the other hand, the metal layer 124persists on the top and sides of the dummy gate 112. On these parts, thesilicon nitride of layers 106 and 116 of the dummy gate and spacers hasprevented siliciding.

[0059]FIG. 3, slightly enlarged relative to FIG. 2, shows thepossibility of pooling the source and drain with other components. InFIG. 3, the locations of the gates of other components have beenoutlined in a chain dotted line.

[0060]FIG. 4 shows the formation of low resistivity accesses to thesource and drain regions. This operation comprises the conformingdeposit of a first, so-called contact, metal layer 130 followed by asecond contact metal layer 132. The first contact metal may be chosenfrom among tungsten or titanium for example.

[0061] The second contact metal, preferably chosen to have greaterresistance to abrasion than the first contact metal, may for example bechosen from among tantalium, tantalium nitride, titanium nitride, . . ..

[0062] In the illustrated example, the overall thickness of the twolayers of contact metal totals the height of the dummy gate or more, sothat it is subsequently possible to perform polishing, stopping at thedummy gate.

[0063] The result of polishing is shown in FIG. 5. It can be seen thatpolishing is stopped precisely at the second layer 106 of material ofthe dummy gate, in this case the layer of silicon nitride.

[0064] The siliciding metal layer 124 comes to be removed from the toppart of the dummy gate, and electric insulation of the source and drainregions can be obtained. It is recalled that, outside the active region,whose length is generally smaller than the length of the gate in adirection perpendicular to the plane of the figures, it is possible touse appropriate etching, in known manner, to fix the limits of theconductor parts and hence to avoid any short-circuiting between theseparts. In addition, insulation is also obtained by means of an oxidationas described below, with reference to FIG. 6 and conducted during asubsequent step of the method.

[0065] Through the use of two different contact materials, an uppersurface 136 with good planarity can be obtained.

[0066]FIG. 6 shows a subsequent step which consists of imparting aninsulating nature to the materials flush with the upper surface 136.During this step, oxidation is performed by subjecting the structure toan oxidizing atmosphere. Oxidation particularly concerns the contactmetals already mentioned in the preceding description. To facilitate thereading of FIG. 6, the oxidized parts are marked with the samereferences as the corresponding non-oxidized parts but are followed bythe letter a. The oxidized parts 124 a, 130 a and 132 a are thereforerespectively the oxidized superficial parts of the metal preserved onthe sides of the gate, and initially used for siliciding the firstcontact metal and the second contact metal. Their oxidation imparts anelectric insulating nature to the metals.

[0067]FIG. 7 shows the structure obtained after removal of the dummygate. Removal is made by selectively attacking the silicon nitride ofthe second layer 106 of the dummy gate, then by attacking thepolycrystalline silicon of the first layer. At the time of this etching,the oxide layer of pedestal 102 may be used as etching stop. This layeris then also removed. The etching agents used may for example be HBr orSF₆ for etching silicon nitride, and HBr+Cl₂ for etching thepolycrystalline silicon. The oxide may be removed with dilute HF. Duringthis step, part of the layers 124 a, 130 a and 132 a is also removed.Therefore, during the oxidation step in FIG. 6, the thickness of theoxide is sized so as to take into account this partial etching of layers124 a, 130 a and 132 a.

[0068] The removal of the dummy gate leaves behind a well denoted 140.

[0069]FIG. 8 shows the fabrication of the final gate. This operationcomprises the formation of a gate insulating layer 148, for example byoxidizing the silicon of the underlying substrate, or by depositing adielectric material, then depositing a layer of gate material 150,preferably in a metal chosen for example from among: W, TaN, W/TiN, Ti,TaN, Cu/TaN, W/Pt, N/Pt, W/Nb or W/RuCa.

[0070] Layer 150 may be a solid layer or optionally made up of acombination of two or more of the materials cited. The thickness of thelayer or layers of gate 150 is sufficient to fill in the well left afterremoval of the dummy gate and to cover the upper plane surface 136 asdefined by polishing.

[0071] A second polishing operation, as shown in FIG. 9, makes itpossible to remove the material of the gate layer 150 above the sourceand drain, so as only to maintain material in the well. The gate, whichis flush with the upper surface 136, is also denoted 150. The endcomponent obtained is a field-effect transistor and has a structure ofdamascene type.

[0072] The figures do not show the fabrication of contact pads on thegate, source and drain. These operations, well known in themselves inthe field of microelectronics are not, in the strict sense of the word,part of the method of fabricating the transistor.

[0073]FIGS. 10 and 11 show the fabrication of another component, amemory in particular, using a structure such as described with referenceto FIG. 7.

[0074] A first gate layer 160 whose thickness is less than the depth ofthe well 140 left by the dummy gate, that is to say less than the heightof the removed dummy gate, is formed above gate insulating layer 148which lines the bottom of the well. The first gate layer 160 also coversthe upper free surface 136 of the structure.

[0075] Above the first gate layer an inter-gate dielectric layer 162 isdeposited, whose thickness, added to the thickness of the first gatelayer, is also less than the height of the dummy gate (removed).

[0076] Finally, a second gate layer 164 is deposited on the inter-gatelayer 162. The thickness of the second gate layer is sufficient,together with the other deposited layers, to fill in the well left afterremoval of the dummy gate.

[0077] It is to be specified that the above-mentioned layers may each beformed of a stack of several sub-layers. In particular, the inter-gatelayer 162 may be formed of a nitride/oxide/nitride stack chosen forhaving a particularly high dielectric constant. The materials chosen forthe first and second gate layers may be those mentioned previously forthe fabrication of the transistor gate.

[0078] Polishing of the gate and inter-gate layers, stopping at themetal oxides 124 a, 130 a, 132 a, makes it possible to obtain astructure such as shown in FIG. 11. It can be seen that the first gatelayer, and the inter-gate layer, have a U shape section along a planeparallel to the plane of the figure substantially extending in asource-gate-drain direction. The second gate layer 154 fills in the Ushape.

[0079] With this particular shape it is possible to increase thesurfaces opposite one another between the first and second gate layerswithout, however, increasing the surfaces opposite one another betweenthe first gate layer and the substrate. Since the first and second gatelayers, after polishing, respectively form the floating gate and thecommand gate of a memory, the structure in FIG. 11 provides a highcapacity between the command gate and the floating gate and a lowcapacity between the floating gate and the channel (substrate). Sincethe source and drain access resistances are also very low on account ofthe use of the contact metal, high frequency functioning for the memorycan be achieved, both for reading and for writing.

[0080] When a transistor or a memory such as described above areintegrated into a circuit, contact points are made in the source, drainand gate regions. These comprise the formation of openings for examplein the oxide layers which cover the source and drain, followed by thepositioning of an interconnection metal in the openings to connect thenon-oxidized contact metal to interconnection lines. Even though suchoperations no longer form part of the fabrication of the components andare well known in themselves, FIG. 12 illustrates an interconnectionoperation between the drain of a memory component such as previouslydescribed and a neighbouring component.

[0081] A layer of insulating material 170 such as SiO₂ is deposited onthe free surface 136 of the components, that is to say the surfaceobtained by the last polishing. This layer prevents short-circuitingbetween an interconnection material (not shown) and other componentparts.

[0082] An opening 172 made in the insulating layer 170 extends throughthe oxidized parts 130 a, 132 a of the first and second layers ofcontact metal to expose the non-oxidized parts 130, 132 of these layers.FIG. 12 shows that the alignment requirements of opening 172 in theinsulating layer 170 are not very high. The opening only needs tocoincide with the chosen source or drain region, without necessarilycorresponding to the centre of this region. The fact that differentmaterials are encountered when making opening 172 accounts for thestaircase bottom of the opening as shown in FIG. 12.

[0083] Cited Documents

[0084] [1] FR-A-2 757 312

[0085] [2] FR-A-2 750 534

1. Method for fabricating an electronic component with self-alignedsource, drain and gate, comprising the following steps: a) the formationof a dummy gate (112) on a silicon substrate (100), said dummy gatedefining a position for a channel (121) of the component, b) at leastone implantation of doping impurities in the substrate, to form a source(118) and a drain (120) either side of the channel, using the dummy gateas implanting mask, c) superficial, self-aligned siliciding of thesource and drain, d) depositing at least one layer of so-called contactmetal (130, 132) having a total thickness greater than the height of thedummy gate, and polishing the metal layer stopping at the dummy gate, e)replacing the dummy gate by at least one final gate (150, 160, 164)separated from the substrate by a gate insulating layer (148), andelectrically insulated from the source and drain.
 2. Method according toclaim 1, in which step d) comprises the depositing of a first metallayer (130) and, above the first layer, a second metal layer (132)having greater mechanical resistance to polishing than the first layer,the thickness of the first metal layer being less than the height of thedummy gate, but the total thickness of the first and second layers beinggreater than the height of the dummy gate.
 3. Method according to claim1 also comprising, before siliciding, the formation of side spacers(114, 116) on the sides of the dummy gate.
 4. Method according to claim3, in which dual-layer spacers are formed comprising an attachment layer(114) in silicon oxide, in contact with the dummy gate, and asuperficial layer (116) in silicon nitride.
 5. Method according to claim2, in which the first metal is chosen from among tungsten and titanium,and in which the second metal is chosen from among TaN, Ta and TiN. 6.Method according to claim 1 comprising, after polishing, superficialoxidation of the metal layer or layers.
 7. Method according to claim 1,in which a solid substrate is used.
 8. Method according to claim 1, inwhich a substrate of silicon on insulator type is used.
 9. Methodaccording to claim 1, in which step e) comprises the removal of thedummy gate, formation of the gate insulating layer (148), depositing atleast one metal layer (150, 160, 162), so-called gate layer, having anoverall thickness equal to or greater than the height of the removeddummy gate, and forming said metal layer.
 10. Method according to claim9 comprising, after the formation of the gate insulating layer (148),the depositing of a first gate metal layer (160), the depositing of atleast one inter-gate dielectric layer (162), and the depositing of asecond gate metal layer (164).